555 Timer Calculator
Calculate Smarter. Work Faster.
Astable, Monostable & Bistable calculator — find 555 timer pulse width, frequency, time high/low and duty cycle from R1, R2 and C1, or see how bistable (flip-flop) mode works.
555 Timer Configuration
Choose the operating mode, then enter the resistor and capacitor values.
No timing resistor or capacitor needed
In bistable mode the 555 is wired as a simple set-reset (SR) latch, with the timing resistor and capacitor removed entirely. External pull-up resistors (RSET, RRESET) may be used on the trigger and reset inputs. Pull Trigger (pin 2) low to set the output high; pull Reset (pin 4) low to reset the output low. The output then simply holds that state until the opposite pin is pulsed — there's no pulse width or frequency to calculate.
| Trigger (pin 2) | Reset (pin 4) | Output (pin 3) |
|---|---|---|
| Pulsed LOW | HIGH | Sets HIGH |
| HIGH | Pulsed LOW | Resets LOW |
| HIGH | HIGH | Holds last state |
| Pulsed LOW | Pulsed LOW | Resets LOW — RESET dominates |
Formula-based ideal timing. Real components have tolerance (some general-purpose electrolytic capacitors are specified at ±20% or worse), and supply voltage or 555 variant (bipolar vs. CMOS) can shift results slightly from this calculation.
Enter values and hit calculate
Ideal-component reference calculation — verify on an oscilloscope for timing-critical designs.
Enter values above to see a breakdown.
555 Timer Formulas Explained
The 555 is one of the most widely produced integrated circuits ever made, used for clock generation, delay timing, pulse generation, and signal oscillation. Internally, it's built around two comparators referenced to 1/3 and 2/3 of the supply voltage, an SR flip-flop, and a discharge transistor — that internal structure is what gives rise to the three external wiring configurations below, each with different timing behavior. The "555" name is historically associated with the classic bipolar 555's internal three-resistor reference divider — three 5 kΩ resistors connected in series between the supply and ground, forming the voltage divider that sets those 1/3-Vcc and 2/3-Vcc comparator thresholds. Modern CMOS 555 variants don't necessarily share this exact internal implementation, though they replicate the same external timing behavior.
Choosing R and C Values in Practice
For a given target time or frequency, the same result can come from many different R/C combinations — a large resistor with a small capacitor, or a small resistor with a large capacitor. In practice, favor a mid-range resistor (a few kΩ to a few hundred kΩ) and pick the capacitor to hit the target time, rather than the reverse: for practical timing designs, many engineers avoid very small capacitors (for example, below roughly 100 pF) because stray/parasitic capacitance becomes significant relative to them — check the specific device datasheet for recommended ranges — while very large electrolytic capacitors bring both wide tolerance and noticeable leakage current, both of which erode timing accuracy. For timing-critical work, choose a capacitor with suitable tolerance and temperature/voltage stability: C0G/NP0 ceramic or film capacitors are often preferable to general-purpose electrolytics where their capacitance range is practical, while other ceramic dielectrics such as X7R or Y5V can vary significantly with applied voltage and temperature.
Monostable wiring: R1 charges C1 from VCC toward the discharge/threshold node; a trigger pulse on pin 2 starts one output pulse of fixed width T = 1.1 × R1 × C1, then the output returns low. Simplified timing schematic — the control-voltage bypass capacitor on pin 5 is omitted here for clarity (see the Common Mistakes section below).
Monostable (One-Shot) Formula
T = 1.1 × R1 × C1, where T is the output pulse width in seconds, R1 is in ohms, and C1 is in farads. Every time the trigger pin is pulsed low, C1 charges through R1 from its initial voltage toward the supply voltage; when it crosses 2/3 Vcc, the internal comparator ends the pulse and discharges the capacitor, resetting the timer for the next trigger. The constant 1.1 comes directly from the RC charging math to reach that 2/3 Vcc threshold, assuming the capacitor starts each cycle fully discharged near 0V, which the discharge transistor ensures in normal operation.
Worked example: R1 = 100 kΩ, C1 = 10 µF. T = 1.1 × 100,000 × 0.00001 = 1.1 seconds. Doubling either R1 or C1 doubles the pulse width, since the formula is a simple product of the two.
Astable (Free-Running) Formula
In astable mode the 555 continuously switches between its threshold states, producing a free-running oscillation between high and low with no external trigger needed. The capacitor charges through R1 + R2 (giving the high time) and discharges through R2 alone (giving the low time):
Time High: Th = 0.693 × (R1 + R2) × C1
Time Low: Tl = 0.693 × R2 × C1
Frequency: f = 1.44 ÷ ((R1 + 2R2) × C1)
Duty Cycle: D = (R1 + R2) ÷ (R1 + 2R2) × 100%
Astable wiring: R1 and R2 together charge C1 through the timing node (giving Th), while R2 alone discharges it back down (giving Tl) — because the charge path always includes the extra R1, Th is always longer than Tl in this basic topology, producing a continuous square-wave output. Simplified timing schematic — the control-voltage bypass capacitor on pin 5 is omitted here for clarity (see the Common Mistakes section below).
Worked example: R1 = 1 kΩ, R2 = 10 kΩ, C1 = 0.1 µF. Th = 0.693 × 11,000 × 0.0000001 = 0.762 ms. Tl = 0.693 × 10,000 × 0.0000001 = 0.693 ms. f = 1.44 ÷ (21,000 × 0.0000001) = 685.7 Hz. Duty Cycle = 11,000 ÷ 21,000 × 100% = 52.4%.
Why duty cycle can't go below 50% in this basic circuit: since Th always includes the extra R1 term that Tl doesn't, Th > Tl for any circuit with R1 > 0 — pushing duty cycle above 50% no matter how small R1 is made relative to R2. Getting a duty cycle at or below 50% needs a diode placed across R2 to give the charge and discharge paths independent resistances; that modified circuit's duty-cycle math then matches the general-purpose Duty Cycle & PWM Calculator on this site.
Worked Example
Monostable: R1 = 100 kΩ, C1 = 10 µF → T = 1.1 × 100,000 × 0.00001 = 1.1 s.
This calculator uses the standard 555 timing equations for the classic astable/monostable topologies above, assuming ideal resistor and capacitor values. Component tolerance, supply voltage, and the specific 555 variant (e.g. CMOS TLC555 vs. bipolar NE555) can shift real-world timing slightly from these formulas — verify on an oscilloscope for anything timing-critical.
Bistable Mode, and Where Each Configuration Is Used
Bistable mode is the simplest of the three: remove the timing capacitor entirely, tie the threshold pin (6) directly to ground so that its input stays held below the 2/3-Vcc threshold and never trips the threshold comparator, and hold the trigger (pin 2) and reset (pin 4) pins normally high through pull-up resistors RSET and RRESET. Momentarily grounding pin 2 (SET) sets the output high; momentarily grounding pin 4 (RESET) resets the output low. With no capacitor to charge or discharge, there's no timing at all — the output simply holds whichever state it was last driven to, exactly like a manual push-button latch or a basic memory element. Note that this describes steady-state behavior only: at power-up, before either input has been pulsed, the initial output state isn't guaranteed and may come up either high or low unless the circuit includes a deliberate startup SET or RESET condition.
Bistable wiring: pull-up resistor RSET with an active-low switch sets the output high via the trigger pin; pull-up resistor RRESET with an active-low switch resets it low via the reset pin; the threshold pin (6) is tied straight to ground and the discharge pin (7) is unused. No timing resistor or capacitor is used — the small 0.01 µF capacitor shown on pin 5 is an optional control-voltage noise bypass only, not a timing component.
On the 555, the reset input is documented as dominant over the trigger input: if trigger and reset are pulled low at the same time, the output is forced — and held — LOW regardless of the trigger state. It's still good practice not to deliberately drive both at once in a real design, but the output behavior itself is well-defined, not a race condition.
| Mode | Typical Application |
|---|---|
| Monostable | Fixed-length delay timers, switch debounce, single-pulse generation from a noisy or bouncy input signal |
| Astable | Clock signal generation, LED flashers, tone/beeper generation, basic square-wave oscillators |
| Bistable | Simple flip-flop / latch, toggle switches, basic memory element, manual set-reset control |
Retriggerable vs. non-retriggerable monostable: retriggering behavior depends on the specific 555 device and circuit configuration, so it isn't accurate to call the standard monostable universally non-retriggerable. In many basic NE555 monostable circuits, a suitable trigger applied during the timing interval can extend or reinitiate the cycle, and the sequence only ends once the trigger pin has been held high for a short period before the interval expires — consult the specific device datasheet for exact behavior. Some applications (a motion-sensor light that should stay on continuously as long as motion keeps being detected) specifically want this retriggerable behavior, where each new trigger restarts the timing period from zero; if your device or design doesn't retrigger as needed, a different IC or additional external logic may be required.
Using astable output as PWM: the basic two-resistor astable circuit gives a fixed duty cycle set by the R1:R2 ratio, not a continuously adjustable one. Simply replacing R2 with a potentiometer does make the duty cycle adjustable, but it changes both duty cycle and frequency together, since R2 appears in both the Th and Tl terms — a diode-separated charge/discharge path (a diode across R2, as described above) combined with a potentiometer is the more standard approach, since it lets duty cycle be adjusted with less coupled effect on frequency. Once you have a target Th and Tl in mind, the Duty Cycle & PWM Calculator on this site handles the resulting duty-cycle and average-voltage math.
Common Mistakes When Designing 555 Timer Circuits
1. Using resistor values far outside the recommended range. Most 555 datasheets suggest keeping timing resistors roughly between 1 kΩ and 1 MΩ — values much lower can push the discharge transistor beyond its comfortable current range, while very high values make timing more sensitive to the chip's own leakage current and PCB leakage effects.
2. Forgetting that real capacitors, especially electrolytics, have wide tolerance. A common electrolytic capacitor can be off by ±20% or more from its printed value — for timing-critical designs, use film or ceramic capacitors with tighter tolerance, or measure the actual capacitance before finalizing component values.
3. Expecting a standard astable circuit to hit exactly 50% duty cycle. The basic two-resistor topology always gives duty cycle above 50% because the charge path (R1+R2) is always longer than the discharge path (R2 alone) — a diode across R2 is needed to get duty cycle at or below 50%.
4. Mixing up which resistor sets which timing interval in astable mode. R1 appears only in the charge/high-time term (through the R1+R2 charge path), but changing R1 still changes the overall period and frequency, not just the high time; R2 affects both the high time and the low time. Increasing R2 alone lengthens both Th and Tl (lowering frequency while keeping duty cycle closer to 50%); increasing R1 alone lengthens only Th (raising duty cycle) while also lowering frequency, since the period Th+Tl grows too.
5. Omitting the control voltage pin (pin 5) bypass capacitor. A small capacitor (commonly 0.01 µF) from pin 5 to ground is standard practice to filter noise on the internal 2/3-Vcc reference — skipping it can make the circuit more susceptible to false triggering or jitter, especially in electrically noisy environments.
6. Assuming every 555 monostable behaves the same way on a second trigger. Retriggering depends on the specific 555 device and circuit configuration — some basic wirings can extend or reinitiate the timing cycle on a mid-pulse trigger, while others effectively ignore it. Check the specific datasheet, and if your application needs guaranteed retriggerable behavior (or guaranteed non-retriggerable behavior), verify it rather than assuming.
7. Not accounting for supply voltage or 555 variant differences. The classic bipolar NE555 and newer CMOS variants (like the TLC555 or ICM7555) can have slightly different threshold behavior and drastically different supply current and minimum operating voltage — check the specific datasheet rather than assuming universal NE555 figures for every 555-family part.
8. Ignoring capacitor discharge path resistance in bistable mode circuits that still have a capacitor present. If a capacitor is left connected from a previous astable or monostable design when converting a circuit to bistable operation, stray charge on it can cause an unexpected initial output state at power-up — remove or fully account for any timing capacitor when wiring a genuine bistable (latch) configuration.
Frequently Asked Questions
What are the common operating configurations of a 555 timer? +
Monostable (one-shot): a trigger produces a single output pulse of fixed width set by R1 and C1. Astable (free-running): the timer continuously oscillates with no external trigger, at a frequency and duty cycle set by R1, R2 and C1. Bistable: with the timing resistor and capacitor removed, the 555 acts as a simple set-reset latch, holding whichever state the trigger or reset pin last drove it to. External pull-up resistors may still be used on those pins, but no timing components are involved.
What is the formula for 555 timer monostable pulse width? +
T = 1.1 × R1 × C1, with R1 in ohms and C1 in farads giving T in seconds. The constant 1.1 comes from the RC charging time needed to reach the 2/3-Vcc internal threshold that ends the pulse.
What is the formula for 555 timer astable frequency and duty cycle? +
Th = 0.693 × (R1+R2) × C1. Tl = 0.693 × R2 × C1. f = 1.44 ÷ ((R1+2R2) × C1). Duty Cycle = (R1+R2) ÷ (R1+2R2) × 100%. All resistances in ohms and capacitance in farads.
Why is the duty cycle of a standard 555 astable circuit always above 50%? +
The capacitor charges through R1+R2 (giving Th) but discharges through only R2 (giving Tl), and since R1 is always positive, Th is always greater than Tl. Getting duty cycle at or below 50% needs a diode across R2 to give the charge and discharge paths separate resistances.
What is 555 timer bistable mode, and why doesn't it need a timing resistor or capacitor? +
In bistable mode, the 555 is wired as a simple SR latch: pulling trigger (pin 2) low sets the output high, and pulling reset (pin 4) low resets it low. External pull-up resistors on those pins are common but play no role in timing. The output then holds that state indefinitely until the opposite pin is pulsed — there's no RC timing network, so there's no pulse width or frequency to calculate.
What resistor and capacitor value ranges give the most accurate 555 timing? +
Most datasheets recommend timing resistors roughly between 1 kΩ and 1 MΩ. For practical designs, many engineers also avoid very small timing capacitors (for example, below roughly 100 pF), since stray capacitance becomes significant relative to them — check the specific datasheet for recommended ranges. Values outside these ranges can push the IC's discharge stage beyond a comfortable current range or make timing overly sensitive to leakage effects, degrading accuracy from the ideal formula.
Why doesn't my built 555 timer circuit match the calculated pulse width or frequency exactly? +
The formulas assume exact component values, but real capacitors (especially electrolytics) can be off by ±20% or more, and resistors are typically ±5%. Supply voltage and the specific 555 variant also shift thresholds slightly. Use tighter-tolerance components for critical designs, and verify actual output on an oscilloscope.
Can a 555 timer's astable output be used as a PWM signal? +
The basic astable circuit gives only a fixed duty cycle set by the resistor ratio, not a continuously adjustable one. With a diode across R2 (or a potentiometer in place of a resistor), the duty cycle becomes adjustable, letting the 555 serve as a simple PWM source for LED dimming or basic motor speed control.
What is the difference between a retriggerable and non-retriggerable monostable? +
Retriggering depends on the specific 555 device and circuit configuration. In many standard NE555 monostable circuits, a suitable trigger applied during the timing interval can extend or reinitiate the cycle, ending only once the trigger pin has been held high briefly before the interval expires — consult the specific datasheet for exact behavior. Devices or configurations explicitly built as retriggerable restart the timing period from zero on every new trigger — useful for something like a motion-sensor light that should stay on as long as retriggering pulses keep arriving.
Should I pick a larger resistor or a larger capacitor to hit a target 555 timing value? +
The same T, frequency, or Th/Tl value can come from many R and C combinations, so favor a resistor in the low-to-mid range (roughly a few kΩ to a few hundred kΩ) and let the capacitor value fall out of the formula, rather than the reverse. As a practical guideline, many engineers avoid very small capacitors (under about 100 pF) since they become sensitive to the circuit's own stray capacitance; check the specific datasheet for recommended ranges. Very large electrolytics bring wide tolerance and leakage current — both degrade timing accuracy. C0G/NP0 ceramic or film capacitors are often preferable to general-purpose electrolytics where their capacitance range is practical, since other ceramic dielectrics (X7R, Y5V) can vary significantly with voltage and temperature.
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